The present invention relates to a process for fabricating semiconductor devices, and more specifically to a semiconductor fabricating process including one or more steps for recovering the crystal damage resulting from ion implantation, and activating carriers.
In semiconductor fabricating processes, various high temperature heat treatments are required to separate or interconnect a plurality of semiconductor devices which are formed in and on a single semiconductor substrate. Usually, ion implantation for forming a LDD (Lightly Doped Drain) structure, or source/drain regions usually results in crystal damage. In order to improve the crystallinity of a semiconductor substrate and to electrically activate implanted acceptor or donor ions, the ion implantation is followed by a step of activation annealing. Furthermore, in order to reduce a contact resistance, a silicide layer of compound consisting of Si and metal, such as refractory metal (W, Mo, Ti, etc.), Pt or Pd, requires a high temperature heating step. Conventional fabricating processes employ, as the activating anneal or high-temperature heat treatment, furnace annealing or rapid thermal annealing (RTA).
With advance in the IC technology, each IC component becomes smaller in size, and a shallower junction is required for source and drain regions, and emitter and base regions. The furnace annealing and rapid thermal annealing make the diffusion deeper, however, and these annealing methods cannot satisfy the demand for device miniaturization and higher packing density. During the activating anneal subsequent to the ion implantation, the diffusion proceeds not only vertically in the direction to deepen the source and drain diffusion regions, but also sideways so as to broaden the lateral dimension. This lateral diffusion tends to increase the possibility of punch-through specifically in a miniaturized MOS transistor having a short gate length. Annealing at a lower temperature can avoid these undesirable diffusion effects and keep shallow implants shallow. In this case, however, the resistivity remains high, the device's current handling characteristic becomes poor, and the transistor is unable to provide required switching performance.
The time required for rapid thermal annealing is not short enough. FIG. 3 shows one example in which the substrate is heated at about 1400.degree. C. The rate of increase of temperature is 100.degree. C./sec, and a rise of temperature takes a considerable time. The duration t during which the substrate is held at the peak temperature is equal to or more than one second, at least. The duration of the peak temperature is still too long to achieve a desired shallow source-drain junction structure in a minute transistor having a gate length (Lg) as short as 0.5.about.0.35 .mu.m, for instance. Moreover, infrared radiation used in RTA is absorbed unevenly by SiO2 films on top of the substrate and other topside films having different infrared absorption characteristics.
Pulsed laser irradiation is another method which can be employed for the activating anneal to form a shallow doped region. The laser pulse energy is absorbed by the surface (about 20 nm) of the semiconductor substrate, so that the pulse laser annealing is possible only at a depth of about 100 nm or less, even if thermal diffusion is taken into account. The temperature increase of the wafer as a whole is very small (about 1.degree..about.2.degree. C.). The pulsed laser annealing is, therefore, suitable for activation annealing to form a shallow LDD structure, or source-drain pair.
In the case of the pulse laser activation annealing, however, the time of heat treatment is very short (t=100 nsec, for instance) as shown by a profile of the substrate temperature during irradiation in FIG. 4. Therefore, it is not possible to clear a silicon substrate 1 of point defects 2 formed at levels deeper than the junction of an ion implanted region 1a, such as a source/drain region. The remaining point defects cause an increase of leakage current given an application of reverse voltage. FIG. 6 shows a relationship between reverse voltage and reverse leakage current in a junction accompanied by such points defects 2. In the example of FIG. 6, only the pulse laser annealing is applied.
This problem can be solved by increasing the power of the laser to heat deeper regions in the substrate. However, this solution deepens and broadens the implant dopant profile as in the conventional furnace annealing or RTA. Furthermore, high energy laser pulses melt the semiconductor surface to a greater depth and damages the flatness or planarity of the semiconductor substrate surface. Low energy laser pulses melt only a very thin surface layer, and allows a flat surface to be immediately formed again.